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ZL62024 4x5 gb/s tia/la receiver data sheet january 2008 page 1 zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2008, zarlink semiconductor inc. all rights reserved. fe atu r e s ? 4 -channel in teg r ated trans impedance a n d li mitin g a m p lifie r ope rates up to 6.25 gb/s ? 12 ua pp recei v er sensitivity f o r 10 -12 ber at 5 g b / s ? s ing l e +3 .3 v supp ly d i s s i pa ting 110 mw pe r chan ne l ? s el ect a bl e a n al o g multi p l e xer provi d e s junc tion te mp e r atu r e , supp ly vo ltage, and r e ce ived s i gna l s t rength fo r each channe l ? i nd ividua l channe l s i gna l de tec t co mpa r e s input s i gna l s t r ength w i th ad jus t ab le threshold ? s que lch automa t ica lly d i sab l es output when input s i gna l s t r ength fa lls be lo w p r og ra mmab le th resho l d ? 2 -wire i n t e rf a c e provi d e s a c ce ss t o i n t e rn al re gi st ers ? c ml output with se lec t ab le p r e - e m phas is and output amp litude contr o l ? 250- mic r on chann e l p i tch ma tches optica l r i bbon fibe r and photod iod e ar ra ys ? i c d i mens ions 2245 x 187 0 u m appli c ation s ? q sfp transce ive r optica l modu les ? p rop r ie ta r y 4 - lane intra - s yste m pa ra lle l optics ? s ing l e data rate ( s d r ) and double data rat e (ddr) i n fini band? ? s ing l e data rate ( s d r ) and double data rat e (ddr) x a ui ? 1 g , 2g, 4g fibe r chan ne l ? p c i exp r e s s 1 . 0 and 2.0 ? g igab it ethe rnet d escrip t i o n t he g r o w ing use of the inte rnet has c r ea ted in c r eas i ng ly highe r de mand fo r mu lti- gb/s i/o pe rfo r mance. t he de mand fo r 100 gb/s bandw id th an d beyond fue l s the g r o w th o f shor t- r each 10 gb/s in fras tru c tu res w i th in h i gh - end te lco and dataco m rou t er s , s w itches, se rve r s and o t her p r opr ieta r y chass i s - to -chass is links . t he trans impedance a m p l ifie r ach i e v es a nomina l 4 g h z ban dwid th o v er a w i de range of photod iode input capac i tan c e . exce llent channel- to -chann e l iso l a t ion ensu r es data in tegrity a t the receiv er sensitivity l i m i ts. a n i n t e rnal circuit p r o v ides the photod iode re ve r s e b i as vo ltage supp ly and senses a v e r age photocu r rent supp lied to the photod iode a r ra y. t he trans impedance a m p l ifie r is ac - c ou p l ed in te rna lly to a h i gh -gain , h i gh -ban dw id th, diff erenti a l, limiting am plifier. t h e limiti ng am plifier prov id e s a dif f e re nti a l b a c k-t e rmin at e d c m l output that can be used to dr ive 5 gb /s per channel transce ive r s o r othe r c m l co mpa t ib le c l ock and data reco ve r y c i r c u i ts . the cml output p r o v ides se lec t ab le pre - e m phas is con t ro l to improv e si gnal quality. t h e limiting am plifier featu r es a c i rcu i t that senses optica l modu lation am plit u d e (o ma) to d e t e rmin e a l o ss of si g n al. a se lec t able ana log mu ltip le xe r p r o v ides junc tion te mpe r atu r e , supp ly vo ltage , and rece ived s i gna l s t rength fo r each chann e l to ena b l e optica l modu le d i agn o s t ic fea t ures. d a ta contro lli ng the za r link z l620 24 is loade d b y a simpl e 2- wire s e ri al s e ri a l int e rf a c e r e d u ci n g t h e nu mbe r o f p i ns requ ired o f a mic r ocontrolle r .
data sheet ZL62024 page 2 zarlink semiconductor inc. tr ansm i t 50 o h m s 50 o h m s 50 o h m s 50 o h m s 50 o h m s 50 o h m s 50 o h m s 50 o h m s 50 o h m s 50 o h m s 50 o h m s 50 o h m s tx _ o ut 0 tx _ o ut 1 tx_ o u t 3 t x _i n 3 _p t x _i n 3 _n tx_i n 1 _p tx_ i n 1 _ n tx_i n 0 _p tx _i n 0 _n rx _ i n0 rx _ i n1 rx_ i n3 rx_ o ut 1 _ p rx_ o ut 0 _ p r x _o u t 0_ n r x _o u t 1_ n rx _ o ut 3 _ p r x _ou t 3_ n zl63044 zl62044 r ecei v e da t a mo ni t o r cl k lo s mon i t o r m i cro con t rol l er in t sd a scl ad c in t r p t dat a cl k cl k da t a gn d gn d gn d pd _ b i a s 0 pd _ b i a s 1 pd _ b i a s 3 in t e r u p t mo d s e l re s e t en ab l e tx _ e n rx _ e n m i cro con t rol l er in t sd a scl ad c mo d s e l re s e t cl k da t a in t e r u p t en ab l e 50 o h m s 50 o h m s tx _ o ut 2 tx_i n 2 _p tx_ i n 2 _ n gn d 50 o h m s 50 o h m s rx _ i n2 rx_ o ut 2 _ p r x _o u t 2_ n pd _ b i a s 2 ZL62024 zl63024 figure 1: a p plicat ion b l ock d i agram u t iliz ing t h e zl63024 vcsel driv er a nd t h e zl62 024 opt i cal r eceiv e r
data sheet ZL62024 page 3 zarlink semiconductor inc. func t iona l d e s c r iption t he za r link z l620 24 rece ive r is a patented 4 - channel, mono lit h i c sige bic m os in teg r ated c i rcu i t that co mb ines h i gh -sens itivity tr ans imped ance a m p lifier s w i th h i gh -ga i n limiting amp lifie r s to p r o v ide a co mp le te 4 - channel optical network ing receiv er , as illus t rat ed in figure 2. ot her f eat ures in c l ude per - channel s i gna l det e ct, chan nel enable , and o u tput pre - e m phas is indepe ndently contro llab le fo r ea ch channel. t he trans impedance a m p l ifie r is a h i gh -bandw id th, low - no ise des ign tha t p r o v ides 4 g h z band w i d t h o v e r a w i de r ange of photod iode input capac itance. t h is enab les cos t -e ffec tive optica l rece ive r modu le des igns b y a llow i ng the use of la rge aper tu re p hotod iodes w i th s i mp lified op tica l coupling and a l ign m ent requ ire m en ts . the tr ans impeda n c e a m p lifie r is insens itive to input capac itance and impedance va r i a t ions to fu r t he r enable robust optica l rece ive r des igns. t he za r link zl620 24 contain s a p r ogra mmab l e s i gna l detec t c i r c u i t that co mpa r es the input optica l modula t ed a m p litude (oma) aga inst a se lec t ab le thr e sho l d to dete r mine a va lid s i gna l . when the inpu t fa lls be low the se le ctab le thresho l d the zl6202 4 as ser t s an e x te rna l in te r r upt and tr ip s the loss of s i gna l chann e l reg i s t e r b i t. t he zl6202 4 a l so has a sque lch featu r e that d i sab l es t he chan nel when a loss o f s i gnal condition is recogn ized. t he trans impedance a m p l ifie r is dc - c ou p l ed inte rna lly to a mu lti- s t age d i ffe r entia l lim itin g a m p lifie r . the limit i ng a m p lifie r featu r es an in te rna l o f fset con t ro l loop to ensu r e peak receive r sens itivity is ma in ta ined fo r a ll input s i gnal s t rengths . the za r l in k ZL62024 c m l output is back - te r m inated and the output co mmon- mod e ma y be ad jus t ed b y varying t he v pp supply en suri ng co m patibility with most 50 ohm l o gic f a milies. the back-t e rminat ed out p ut featu r es an ad jus t ab le ou tput a m p litude contro l and pr og ra mmab le p r e - e m phas is c i r c u i t fo r d r ivin g loss y tr ans mis s i on lines . t he zl6202 4 p r o v ides ana log d i agnostics fo r rece ived s i gna l s t reng th ( r ssi) , supp ly vo ltage, and junc tion te mpe r atu r e . d i agnostics a r e p r o v ided b y a p r opo rtiona l cu r r ent o r vo ltage th rou gh a s i ng le p r og ra mmab le output. t he za r link zl620 24 t i a/la p r o v ides a se r i a l d i g i ta l in ter f ace that a l lo w s inte rnal r e g i s t e r s to be p r og ra mmed and mon i to red as seen in f i gu re 3. the s i mp le 2 - w i r e in te r f ace a llow s co mmon l y a v a i lab l e mic r o c ontro lle rs to a c cess r e g i s t e r s fo r de vice op timiza tion and ana log d i agnostics . f o r ease o f manufac tu r i ng, the za r link zl6202 4 featu r es an a lign m en t c i r c u i t used to optimiz e the optica l cou p ling in to photo d i odes . the a lign m ent c i r c u i t is a c tiva ted when the power supp ly vo ltage is se t to 2.0 v; und e r these cond itions the mo n i t o r ou tput sour ces a cu r r ent that is p r opo r t ion a l to the to ta l detec to r photocu r rent.
data sheet ZL62024 page 4 zarlink semiconductor inc. det_ bi as3 ti a r x _o u t 3_p r x _o u t 3_n ti a rx _o ut 0 _ p rx_ o ut 0_ n li m i t i ng a m p l if ie r rx_en rx_i n 0 rx_i n 3 det_bi a s 1 rx_ e n rx _ e n det_ bi as0 ch 1 1 sq_ e n sq1 1 v3 v v3vi vp p vpp gn d ac t i v e al i gnm ent pow e r s uppl i e s vp p i n t e rn al r e gi st er s gl o bal : cl e a r los l o s confi g ure s q ue l c h confi g u r e m o n i t o r confi g ure cha nnel : en ab l e o u t p ut am pl i t ude pr e e m p h c o nt r o l si gnal d e t e c t and squel c h r s s i 0- 11 m o ni t o r: t e m p eratu r e s u ppl y vol t a g e op t i c a l p o we r st atus: c h a nne l l o ss of si gn al mo n i t o r glo bal ch0 -11 gl o b a l gl o b a l lo s0 - 1 1 rss i 0- 11 r ssi 11 ch0 glo bal r ssi 0 ch 0 ch 1 1 sq0 si gn al det e c t lo s 0 - 1 1 / s q 0-11 g l o bal glo b a l li m i t i ng a m p lifie r clk da t a figure 2: si mplifi e d blo ck di ag ram of the zl 620 24
data sheet ZL62024 page 5 zarlink semiconductor inc. ph ot o n ics interface t he zl6202 4 p r o v ides re ve rse photodiode b i as cur r en t th rough isola t ed det_ bias pads. each pad is indepen dent of each ot her. they are locat ed on adjac ent s i des of e a ch tia i nput ensur i ng compatibility w i th both iso l a t ed aper tu re and co mmon - ca thode phot od iode a r ra ys. an y det_bias pad ma y be used w i th any ad jacen t t i a input. no te that the r s si mon i t o r featu r e r equ ires iso l a t ed aper tu re con f igu r ations . si gnal detect t he zl6202 4 has indep en dent s i gna l de tect c i r c u i ts fo r each chan ne l. the cha nne l s i gna l de tec t c i r c u i ts co mpa r e the input optica l modu la tion amp litude (o ma) aga ins t a pr og ra mmab le th re shold to dete r mine a va lid s i gnal. the th resho l d ma y be ad jus t ed us ing the sd_ t h [ 1:0 ] reg i s t e r b i ts and the h y ste r es is ma y be in c r eased w i th the sd_h yst reg i s t er b i t. when the inpu t s i gna l fa lls be low the p r og ra mmab le th resho l d, the c i r c u i t asse r t s the e x te rna l in te r r upt( s ) and as ser t s the c h _los reg i ste r b i t. th e e x te rna l int e r r upt w ill r e main asser t ed until the optical input ex ceeds t h e loss of s i gnal t h reshold while t he c h _los regis t er bit w ill r e main as sert ed until t h e c l ear int e r r upt sequence is ex er c i sed us ing t he 2- w i re in te r f ace. t he po la r i ty of sd , sd0, and los11 pad s ma y be con t r o lled th roug h the global reg i s t e r and the output style ma y be configu r ed as e i th e r c m o s o r open-d r a i n w i th the sd_o d r e g i s t e r b i t. sq uelch t he zl6202 4 sque lch mod e fo r c es the diffe rentia l ou tput s o f an individ u a l chann e l to a log i c - ze ro when the s i gnal detec t c i r c u i t repo r t s a loss o f s i gnal. the sq_en b i t a l low s the sque lch func tion to be enabled/d i sab l ed fo r each channel. the sq_ sel reg i s t e r b i t fo rces the outputs of sque lch ena b l ed ( s q_en =1 ) chann e l s to a log i c - ze ro fo r tes t purposes . diffe r e ntial data outputs t he d i ffe r entia l output a m plitude for each chann e l is contro lled w ith the o a c [ 1 : 0] r e g i s t e r b i ts . each in c r e m ent in o a c p r o v ides appro x ima t e l y 10 % inc r ease in output a m p litude . t he p r e - e m phas is featu r e o f the zl6202 4 pro v ides var i ab le peak ing contro l to o p timize the d i ffe r entia l output wa ve fo r m . th ree ind i vidua l con t r o l ( p re[2 :0]) r e g i s t e r b i ts p r o v ide p r e-emphas is d i sab l e and se ven adjus tab l e edg e pea k i ng se ttings . each chann e l ma y be contr o lled sepa rate ly. p o w e r s upplie s a nd ground t he zl6202 4 ic has th ree powe r supp lies and two sep a rate g r ounds. the v3vi po wer supply is fo r the t i as , the v3v powe r supp ly is fo r the las, and the vpp powe r supp ly is fo r the c m l output s t ag es . the g n d3vi g r ou nd is fo r the t i as and the gn d3 v g r oun d is fo r both th e limiting a m p lifie rs and th e c m l output stages. powe r supp ly decoup ling is r e co mmended. activ e alignment f o r ease o f manufac tu r i ng, the zl620 24 featu r es an a lign m ent c i r c u i t u s ed to optimiz e the optica l coup ling in to the photo d i od es . the a l ignmen t c i r c u i t is ac tiva ted when the powe r supp ly vo ltage set to 2. 0 v. identification code t he zl6202 4 p r o v ides re vis i on con t ro l with the addressab l e id co de reg i s t er . the 8 b i t reg i s t e r p r o v ides a unique va lue fo r each za r link p r oduct and ic r e vis i on.
data sheet ZL62024 page 6 zarlink semiconductor inc. monitor t he mo n i tor [ 7 : 0 ] reg i s t e r b i ts se lec t the output of the analog mu ltip le xe r . the mu ltip le xe r ou tput ( m o n it o r ) sou r ces an ana log cu r r en t o r vo ltage tha t is p r opo r tion a l to the se lected d i agnostic pa ra mete r . pa ra me te rs include re ce ived s i gna l s t reng th ind i ca tor ( r ssi) , junction te mpe r a t u r e , and powe r supp ly vo ltage as de fined in tab l e 1. an e x te rn a l 4k oh m shunt res i s t o r shou ld be con nec ted to monitor. please note that the rssi featu r e requ ires that each photod iode ca thod e be se pa rate . the cir c u i t does not suppor t co mmon- cathode photod iod e configu r a t ions . res e rve d 4- 2 3 jun c t i on te m p e r atu r e ( p o r sta t e) 24 po w e r supp ly vo ltage m o n i to r (v cc/ 2 ) 25 f a ctory test 26 res e rve d 27 -30 open cir c u i t st ate ( h igh im pedance ) 31 d e t_ bi as3 photo cu r r en t 3 d e t_ bi as2 photo cu r r en t 2 d e t_ bi as1 photo cu r r en t 1 d e t_ bi as0 photo cu r r en t 0 d esc r i p t i o n s e tting tabl e 1: mo nitor di ag nosti c p a rameters unit equat i on d escript i on ua ipd = imon ito r c hann e l phot o cu r r ent v vcc = vm o n itor * 2 po we r supp ly vo ltage c t j unc = ( v mon i to r - 1 .456 v) / (0 .005 v/c ) junc tion te mpe r atu r e tabl e 2: mo nitor equ a tion s
data sheet ZL62024 page 7 zarlink semiconductor inc. 2- w i re digit a l inter f ac e controller glob a l re gister channe l re gister monitor re gister idcod e re gister sta t us re gister in te r r up t res e t da ta clock ic # 0 da ta clock 2- w i re digit a l inter f ac e controller glob a l re gister channe l re gister monitor re gister idcod e re gister sta t us re gister in te r r up t res e t da ta clock ic # 1 digital co ntrol t he za r link ? z l620 24 t i a/la p r o v ides a se r i a l d i g i ta l in ter f ace that a l lo w s inte rnal r e g i s t e r s to be p r og ra mmed and mon i to red as seen in f i gu re 3. the s i mp le 2 - w i r e in te r f ace a l lo ws co mmonly a v a ilab l e mic r ocontro lle rs to acces s reg i s t e r s fo r device optimiz ation and analog d i agnostics . t he 2 - w i re in te r f ace is in tended fo r use in a ma ste r - s la ve bus con f igu r ation . a mic r o c ontro lle r is the mas t e r and the za r link ic is the s l a v e . t he 2 - w i re bus cons is ts o f a unid i re c t ion a l c l ock that is d r iven b y th e mas t e r and a b i d i re ctional da ta po rt that ma y be d r iven b y e i the r th e mas t e r o r the s l a v e . the data por t ( d at a) cons is ts o f a c m o s input and an open-d r a i n output w i th an in te rn a l pu ll-up res i s t o r and the clo c k input ( c lk) is c m os. t he bus configu r ation suppor ts mu ltip le addressab l e s l a v e de vices . t he zl6202 4 has two address inpu ts (ad r s 0 and ad r s 1 ) that ma y be used to se t the phys i ca l add r ess o f the ic ( a d d r ess[3:0]) . the r e a r e 8 un ique ad d r esses a v a ilab l e fo r the zl630 24 and 8 un ique addre s ses fo r the z l620 24 fo r up to 16 ic s on a s i ng le 2 - w i r e bus . the ad rs0 and ad rs1 tr i- leve l inputs maybe connecte d to vc c , g r oun d, o r no connected ( n c ) . th e phys i ca l ic addres ses a r e shown in tab l e 3 . figur e 3: blo c k di ag r a m of 2- w i r e bu s 1111 gnd vcc 1100 gnd gnd 1101 vcc gnd 1110 nc vcc 1000 vcc vcc 1011 nc gnd 1010 vcc nc 1001 gnd nc 1000 nc nc a d dre ss[ 3: 0] ad r s 0 ad r s 1 ta ble 3 : phy s ical ic a ddress se t t i ngs
data sheet ZL62024 page 8 zarlink semiconductor inc. t h e z l6202 4 has five addressab l e reg i s t e r s as defined in table 4. each reg i s t e r can be accessed indep end ently b y its spec ific r e g i s t e r address ( r eg ister [ 2 : 0]) . it is necessa r y fo r the ma s t er to in itia te and te r m inate w r ite or r ead opera t ions w i th the e x ac t reg i s t e r length . a reg i s t er w r ite transac tion is in itia ted b y the ma ste r w i th a s t a r t seq uence fo llo w ed b y a ph ys ica l ic address ( a d r e ss[3 :0]) , a reg i s t er add ress ( r eg ist e r [ 2:0 ] ) , w r ite ind i cator ( w r [0 ]=0 ) a nd reg i ste r payload data. the w r ite transac tion is co mp le ted b y the mas t e r w i th a s t op seque nce as show in tab l e s 5 and 6. f i gu re 4 sho w s a timing d i ag ra m for a reg i s t e r w r ite opera t ion. the b i nar y input is c l oc ked in to d a ta on the r i s i n g edge of cloc k. it is impo r t ant to ha ve g litch -free dat a s i gna l wh ile clk is h i gh to a v o i d fau l ty sta r t o r s t op cond itions . the stop condition a l so se r v es as the d i g i ta l rese t f o r the d i g i ta l in te rface contro lle r. tabl e 4: reg i ster definiti ons r ead on ly r ead on ly re a d /write re a d /write re a d /write ty p e 100 8 sta t us 011 8 idcod e 010 32 channe l 001 8 monitor 000 16 glob a l a d d r ess r e gist e r [ 2 :0 ] numb er of b i t s reg i ster stop r e gi st er dat a ( 8 -7 2 bi t s ) w r [0 ]=0 register[2: 0 ] addre s s[ 3: 0] start stop condition , a r i s i ng ed ge on d a ta w i th cloc k h i gh te r m inates the 2 - w i re tr ansac tion and rese ts th e d i g i ta l in te rface contro lle r stop r e g i s t e r data . pa yload mus t equal to the length o f th e reg i s t e r (8 -32 b i ts ) re gi st er d a t a r ead/w r ite ind i cato r . w r [0 ]=0 fo r the wr ite opera t ion wr[0] add r ess fo r inte rna l reg i s t e r s ( g lobal , mo n i t o r, ch an nel , idc o de, and st at us) re gsiter[ 2 :0] ph ys ica l address o f s l a v e . d e te r m ined by ad r s 1 and ad rs0 conn ec tions ( v c c , n c , o r gnd) addres s[ 3: 0] st ar t condition, initialed by the mast er , and cons is t s of a f a lling edg e on data while clock is high start d escript i on field a 3 a 2 a 1 a 0 r 2 r 1 r 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d n-1 d n ? wr st art stop data clock ? ta ble 5 : re gis t er w r ite se que n ce tabl e 6: des c ription of fi eld s in write s e qu en ce figure 4: re gister write timing di agram write sequence
data sheet ZL62024 page 9 zarlink semiconductor inc. a reg i s t er read transac tion is in itia ted b y the mas t e r with a s t ar t sequence fo llo w ed b y a ph ys ica l ic address ( a d r e ss[3 :0]) , a reg i s t er add ress ( r eg ist e r [ 2:0 ] ) , a nd a w r ite ind i ca to r ( w r [0]= 1 ) as seen in table 7. the data payload that fo llo w s is a l wa ys in s i ng le b y te un its . afte r r eading each b y te, the ma s t e r mus t send an ac k b i t to continue read ing the contents o f a reg i s t e r o r a na ck a f te r the co mp le te reg i s t e r has been read. a s t op sequence f o llow i ng t he na c k w ill ter m inat e t he transa c tion. a timing d i ag ra m fo r a read tr ansaction is shown in f i gu re 5 . the b l ue -h igh l ighted (b yte_1 an d b y te_n) sec t ions in the dat a w a vefo r m indic a te that the b i d i re ctional d a t a por t of the ic is in output mode. the re ma inder o f the time , both cl o c k and dat a o f the ic ar e in input mode. all r e g i s t er s a r e se t to defau lt va lues after the ic is pow e r ed on. these va lues are known as po wer on re set ( p o r ) va lues and ma y be seen the the reg i s t e r defin ition tab l es 10 -14. the po r r e g i s t e r va lues ma y be obse r ved b y read ing a reg i s t e r afte r a po w e r c y c l e . reg i s t e r s ma y be read repea tably w i thou t d i s t u r b i ng the co nt e n t s o f t h e re gi st er. in add ition to r e g i s t e r acces s , a spec ia l 2 - w i re seque nce a l lo ws th e user to c l ear the stat us reg i s t er . the in stru ction sequence is sho w n in tab l e 8 and the timing d i agra m is sho w n in f i gur e 6. w r [0 ]=1 s top nack ? ack data (8 bits) ack data (8 b its) register[2: 0 ] addre s s[ 3: 0] start ta ble 7 : re gis t er read se que n ce a 3 a 2 a 1 a 0 r 2 r 1 r 0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 ac k d 0 ? d 6 d 7 na c k wr st art stop data clock b y t e_1 by te _n ? figure 5: re gister read timing di agram a 3 a 2 a 1 a 0 r 2 r 1 r 0 wr st art stop data clock stop w r [0 ]=0 register[2: 0 ] addre s s[ 3: 0] start tabl e 8: cl ea r status regi ster s e qu en ce read sequence clear status reg i ster sequence figure 6: cl e a r st atus reg i ster tim i ng di agram
data sheet ZL62024 page 10 zarlink semiconductor inc. t he reg i s t er r ead, reg i s t e r w r ite , and c l ea r st at us reg i s t e r 2 - w i re tr ansactions sha r e the sa me timing r equ ire m ents . f i gu res 7 and 8 sho w c r itica l timing re la tionsh i ps an d table 9 p r ovide s wo rs t case timing . a 3 a 2 a 1 a 0 r 2 r 1 r 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d n-1 d n ? t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 wr st art stop data clock ? critical ti ming figure 7: re gister write s e qu en ce w i th timing relation sh ip s a 3 a 2 a 1 a 0 r 2 r 1 r 0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 ac k t 12 d 0 ? d 6 d 7 t 10 t 10 t 11 na c k wr st art stop data clock b y t e_1 by te _n ? figure 8: re gister read s e qu en ce w i th timing relation sh ip s la st clo ck to stop in read sequence r ead data de lay f r o m clo c k r ead data a v a ila b l e to clo ck edge be tw een cont r o l sequen ce s d a ta = l o w be fo re st op cond it ion last clock to l a st w r it e d a t a tr a n sition c l o ck pe r i od clock low clock high wr ite data to clock hold time wr ite data to clock set time st art c o n d ition t o first clock tra n sition d esc r i p t i o n 2.6 t 10 2.1 t 11 0.5 t 12 22.0 t 9 0.1 t 8 34.0 t 6 6.0 t 7 7.0 t 5 17.0 t 4 0.5 t 3 1.2 t 2 0.2 t 1 wo r s t c ase ti mi n g ( n s ) sy m b o l ta ble 9 : w o rs t case timing f o r 2 - w i re tra n sac tions
data sheet ZL62024 page 11 zarlink semiconductor inc. not e 1: all re gister bits ar e ass e rt e d b y a lo gic lev e l ?1? u n less ot h e r w ise s p ecified n o te 2 : re se r v ed b i t s shou ld a l w a y s be p r og ra m m e d w i t h po r va lue s du r i ng w r it e ope r a t i on s r e se r v ed fo r fu tu re u s e , see no te 2 0 res e rve d 5 r e se r v ed fo r fu tu re u s e , see no te 2 0 res e rve d 6 se le ct s i / o sty l e fo r a ll s d /lo s pad s. 1 = open -d r a in, 0 = c m o s 0 sd_ o d 7 se le ct s ty pe o f sque lch , 0 = no r m a l sque lch, 1 = for c e d sque lch , g a t e d b y chan n el s q _en re gi ster bit 0 sq _ sel 8 d i sa b l e s te m p e r atu r e slope co m pen sa t i on 0 tc_di s ab l e 9 r e se r v ed fo r fu tu re u s e , see no te 2 1 res e rve d 10 r e se r v ed fo r fu tu re u s e , see no te 2 1 res e rve d 11 r e se r v ed fo r fu tu re u s e , see no te 2 0 res e rve d 12 r e se r v ed fo r fu tu re u s e , see no te 2 1 res e rve d 13 r e se r v ed fo r fu tu re u s e , see no te 2 0 res e rve d 14 r e se r v ed fo r fu tu re u s e , see no te 2 0 res e rve d 15 0 0 1 0 1 po r sd_ i nv sd_h y s t[ 0 ] sd_h y s t[ 1 ] s d _t h [ 0] s d _t h [ 1] na m e c hange s the po la r i ty o f the s d outpu t in te r r up t s 4 s i gna l dete c t hy ste r y s is 3 s i gna l dete c t hy ste r y s is ? m sb 2 s i gna l dete c t th re sho l d 1 s i gna l dete c t th re sho l d ? m s b 0 d esc r i p t i o n , see n o te 1 bit ta ble 10 : glob a l regist e r de f i nit i on. re gis t er ty pe = read/w r i t e , a ddre ss register [ 2 :0 ] = 000 - - - 0 0 0 0 0 1 0 1 po r s e e bits 0 - 7 s e e bits 0 - 7 s e e bits 0 - 7 r e se r v ed fo r fu tu re u s e , see no te 2 e n a b les s q u e lch cir c uit or f o rc es sq u e lch co n d itio n, se e gl oba l r e gister s q _s e l bit p r e - e m pha sis co nt r o l fo r d i f f e r en t i a l ou tput s p r e - e m pha sis co nt r o l fo r d i f f e r en t i a l ou tput s p r e - e m pha sis co nt r o l fo r d i f f e r en t i a l ou tput s ? msb c hanne l ou tput a m p lit ude cont ro l c hanne l ou tput a m p lit ude cont ro l ? m sb c hanne l enab le d esc r i p t i o n , see n o te 1 3 2 1 0 0 0 0 0 0 0 0 chan s e e bits 0 - 7 s e e bits 0 - 7 s e e bits 0 - 7 res e rve d sq _ e n pre [ 0] pre [ 1] pre [ 2] oac[0] oac[1] ch_en na m e n o te 2 : re se r v ed b i t s shou ld a l w a y s be p r og ra m m e d w i t h po r va lue s du r i ng w r it e ope r a t i on s not e 1: all re gister bits ar e ass e rt e d b y a lo gic lev e l ?1? u n less ot h e r w ise s p ecified 24 -31 16 -23 8- 1 5 7 6 5 4 3 2 1 0 bit tabl e 1 1 : ch annel r e gi ste r d e finitio n . r e gi ste r ty pe = r e a d / w rite, addr e s s r e g i st e r [2:0] = 0 1 0
data sheet ZL62024 page 12 zarlink semiconductor inc. - - - 0 0 po r s e e bits 0 - 1 s e e bits 0 - 1 s e e bits 0 - 1 r e se r v ed fo r fu tu re u s e c hanne l lo ss o f sig n a l ind i ca to r d esc r i p t i o n , see n o te 1 3 2 1 0 0 chan s e e bits 0 - 1 s e e bits 0 - 1 s e e bits 0 - 1 res e rve d c h _lo s na m e not e 1: all re gister bits ar e ass e rt e d as logic level ? 1 ? unless other w ise s p ecified 6- 7 4- 5 2- 3 1 0 bit ta ble 12 : sta t u s re gis t er de f i nit i on. re gis t er t y p e = rea d only , a ddress register [2 :0 ] = 100 1 1 1 0 1 0 0 1 po r i c ident if ica t ion code i c ident if ica t ion code i c ident if ica t ion code i c ident if ica t ion code i c ident if ica t ion code i c ident if ica t ion code i c ident if ica t ion code i c ident if ica t ion code ? m sb d esc r i p t i o n idcod e [ 0 ] idcod e [ 1 ] idcod e [ 2 ] idcod e [ 3 ] idcod e [ 4 ] idcod e [ 5 ] idcod e [ 6 ] idcod e [ 7 ] na m e 7 6 5 4 3 2 1 0 bit tabl e 13: idcode regi s t er definitio n . regi ster ty pe = read only , a ddres s r e gister[ 2 :0 ] = 011 n o te 1 : re se r v ed b i t s shou ld a l w a y s be p r og ra m m e d w i t h po r va lue s du r i ng w r it e ope r a t i on s m o n i to r outpu t cont r o l 0 monitor [ 2] 5 m o n i to r outpu t cont r o l 0 monitor [ 1] 6 m o n i to r outpu t cont r o l 0 monitor [ 0] 7 1 1 0 0 0 po r monitor [ 3] monitor [ 4] res e rve d res e rve d res e rve d na m e m o n i to r outpu t cont r o l 4 m o n i to r outpu t cont r o l ? m sb 3 r e se r v ed fo r fu tu re u s e , see no te 1 2 r e se r v ed fo r fu tu re u s e , see no te 1 1 r e se r v ed fo r fu tu re u s e , see no te 1 0 d esc r i p t i o n bit tabl e 14: m o nit o r reg i ster definiti on. regi ster t y pe = read / w rite, addre ss reg i st e r [2:0] = 001
data sheet ZL62024 page 13 zarlink semiconductor inc. absol u te maximum ratings t he ic shou ld be used w i th in the limits spec ified in ta b l e 15 . exceed ing the spec ified limits ma y impa ir the use f u l life of the co mpon en t and the device ma y no longer pe r f or m to the spec ifica t ions w i th in th is da ta sheet. functiona lity a t o r abo ve the va lues lis ted is no t imp lied . ta ble 15 : a b s o lute maximum ra t i ng note 1: to an y vo ltage be tween 3.3 v a nd g r ound recommen d ed o p erating co n d iti o ns tabl e 16: recomm end e d op erating conditions dc characteristics ( v 3 v i=v3v=3.3 v +/- 1 0 % , vpp=3 . 3 v + / - 10%, t j unc = 0 -100 c ) tabl e 17: ti a detector i n terface c 150 -65 storage tempe r ature t st g c 125 junction temp e r ature t junc 60 secon d dur ation c 260 die attach tem perature t a ttach esd on all p i n s kv 2 esd toleranc e, (hbm) esd hb m see note 1 ma 50 -50 output short circuit current i sh or t ma 2 input current i in v +3 .6 3 3.3 -0.5 ic suppl y volta g e v3vi, v3v, vp p rema rks units max ty pic a l min. desc rip t io n sy mbol ma 1 detector current i de t _ bi a s v 2.5 detector bias v o ltage v de t _ bi as ohms 50 input imped an ce z input ff 600 detector capac itance c de t v 0.5 dc voltag e pre s ent at rx_in v input rema rks units max ty pic a l min. desc rip t io n sy mbol all chan nels d i sable d ma 3 v3 vi=v3 v =vp p =3 .3 v ma 140 suppl y curr ent icc all chan nels d i sable d mw 10 v3 vi=v3 v =vp p =3 .3 v mw 460 po w e r diss ipati o n p dis f o r 1.8v cml operati o n v 1.89 1.8 1.71 f o r 2.5v cml operati o n v 2.75 2.5 2.25 f o r 3.3v cml operati o n v 3.63 3.3 2.97 cml output su ppl y ran g e vpp f o r 1.8v cml operati o n v 3.465 3.3 3.135 f o r 2.5/3.3v cml operati o n v 3.63 3.3 2.97 positive sup p l y range v3vi, v3v rema rks units max ty pic a l min. desc rip t io n sy mbol
data sheet ZL62024 page 14 zarlink semiconductor inc. tabl e 18: li miting ampli f ier note 1: fo r 1.8v c m l opera t ion, the output mu st be d c - coup led to a c m l inpu t tabl e 19: cmos i/ o ac characteristics ( v 3 v i=v3v=3.3 v +/- 1 0 % , vpp=3 . 3 v + / - 10%, t j unc = 0 -100 c ) ta ble 20 : trans i mpeda n ce a m plif ier note 1: c de t = 450 ff , 6 . 25 gb /s pr bs23 pattern , ber 10 -12 tabl e 21: li miting ampli f ier note 1: r i se and fa ll times measu r ed 20% to 80% t e rminated to vpp ohms 50 t e rmination re sistance r term mv pp 250 singl e-en ded o u tput amplitu d e v am p_sin g mv pp 500 differentia l out put amplitu d e v am p_d i ff rema rks, see note 1 units max. ty pic a l min. desc rip t io n sy mbol i oh = 100 a v 0.2 lo w - l e vel o u tp ut voltage v ol i oh = -100 a v v3v-0.2 high- leve l outp u t voltage v oh v in = 0 v or v in = vdd a +/-5 input current i in v ou t <= v ol (m ax ) v 0.8 -0.3 lo w - l e vel i nput voltage v il v ou t >= v oh (m in) or v v3v+0.3 2 high- leve l inp u t voltage v ih rema rks units max. ty pic a l min. desc rip t io n sy mbol ma pp 1 input saturatio n level i sa t see note 1 a rms 0.7 input referred c u rrent nois e i in ghz 4 3db ban d w i d th f 3db see note 1 a pp 12 receiv er sensi t ivit y i sen rema rks units max. ty pic a l min. desc rip t io n sy mbol gb/s 6.25 data rate d r ps 60 fall time t f ps 60 rise time t r khz 175 lo w - freq uenc y cutoff f c u to ff rema rks units max. ty pic a l min. desc rip t io n sy mbol
data sheet ZL62024 page 15 zarlink semiconductor inc. si gnal pi n definitions tabl e 22: sig n al pin defin i tions d a ta fo r 2 - w i r e in ter f ac e , s ee no tes 1 and 4 input=c mo s ou tput=ope n - d r a i n bi- d i rec t iona l 21 data ind i ca tes s t atus of a ll chan ne l s i gna l detec t c i r c u i ts . see no tes 2, 3 , and 4 digit a l ou tput 22 sd enab les h i gh -speed chann e l s. see no tes 1 and 4 digit a l input 23 rx _ e n t i a +3 .3v po w e r supply supp ly - 24 v3 vi t i a +3 .3v po w e r supply supp ly - 25 v3 vi g r ound fo r tia g r ound - 26 gnd3 vi g r ound fo r tia g r ound - 27 gnd3 vi g r ound fo r tia g r ound - 28 gnd3 vi pho t o d i ode bia s ana l og - 29 d e t_b i as0 c hann e l 0 t i a inpu t ana l og input 30 rx _in 0 pho t o d i ode bia s ana l og - 31 d e t_b i as1 c hann e l 1 t i a inpu t ana l og input 32 rx _in 1 pho t o d i ode bia s ana l og - 33 d e t_b i as2 c hann e l 2 t i a inpu t ana l og input 34 rx _in 2 pho t o d i ode bia s ana l og - 35 d e t_b i as3 se ts ic phys i ca l add r ess . c onnect to +3 .3 v, g r ound or nc tri- lev e l input 20 adrs 0 g r ound fo r limitin g a m p lifie r and c m l o u tput dr ive r g r ound - 17 gnd3 v g r ound fo r limitin g a m p lifie r and c m l o u tput dr ive r g r ound - 18 gnd3 v c l oc k input fo r 2 - w i re in te r f ace . see notes 1 and 4 digit a l input 19 cl k g r ound fo r limitin g a m p lifie r and c m l o u tput dr ive r g r ound - 1 gnd3 v g r ound fo r limitin g a m p lifie r and c m l o u tput dr ive r g r ound - 11 gnd3 v d i ffe rentia l output data fo r chann e l 0, neg a t ive digit a l ou tput 10 r x _o u t 0_n d i ffe rentia l output data fo r chann e l 0, positive digit a l ou tput 9 r x _o u t 0_p + 1 .8 /2.5 /3.3 v c m l output powe r s upp l y supp ly - 14 vp p + 1 .8 /2.5 /3.3 v c m l output powe r s upp l y supp ly - 13 vp p ana l og mu ltiple xe r outpu t. see no te 2 ana l og ou tput 12 monitor l i miting a m p lifie r +3 .3v pow e r supply supp ly - 15 v3 v l i miting a m p lifie r +3 .3v pow e r supply supp ly - 16 v3 v d i ffe rentia l output data fo r chann e l 1, neg a t ive digit a l ou tput 8 r x _o u t 1_n d i ffe rentia l output data fo r chann e l 1, positive digit a l ou tput 7 r x _o u t 1_p d i ffe rentia l output data fo r chann e l 2, neg a t ive digit a l ou tput 6 r x _o u t 2_n d i ffe rentia l output data fo r chann e l 2, positive digit a l ou tput 5 r x _o u t 2_p d i ffe rentia l output data fo r chann e l 3, neg a t ive digit a l ou tput 4 r x _o u t 3_n d i ffe rentia l output data fo r chann e l 3, positive digit a l ou tput 3 r x _o u t 3_p g r ound fo r limitin g a m p lifie r and c m l o u tput dr ive r g r ound - 2 gnd3 v d escript i on st y l e i/o pa d n o . pa d
data sheet ZL62024 page 16 zarlink semiconductor inc. c l oc k input fo r 2 - w i re in te r f ace . see notes 1 and 4 digit a l input 48 cl k d a ta fo r 2 - w i r e in ter f ace , see no tes 1 and 4 input=c mo s ou tput=ope n - d r a i n bi- d ire c tional 46 data ind i ca tes s t atus of a ll chan ne l s i gna l detec t c i r c u i ts . see no tes 2, 3 , and 4 digit a l ou tput 45 sd c hann e l 3 t i a inpu t ana l og input 36 rx _in 3 pho t o d i ode bia s ana l og - 37 d e t_b i as4 g r ound fo r tia g r ound - 38 gnd3 vi g r ound fo r tia g r ound - 39 gnd3 vi g r ound fo r tia g r ound - 40 gnd3 vi g r ound fo r tia g r ound - 41 gnd3 vi t i a +3 .3v po w e r supply supp ly - 42 v3 vi t i a +3 .3v po w e r supply supp ly - 43 v3 vi enab les h i gh -speed chann e l s. see no tes 1 and 4 digit a l input 44 rx _ e n se ts ic phys i ca l add ress . c o nnect to +3 .3v, g r ound, o r nc tri- lev e l input 47 adrs 1 g r ound fo r limitin g a m p lifie r and c m l o u tput dr ive r g r ound - 49 gnd3 v g r ound fo r limitin g a m p lifie r and c m l o u tput dr ive r g r ound - 50 gnd3 v limiting am plifier +3. 3 v su pply supp ly - 51 v3 v limiting am plifier +3. 3 v su pply supp ly - 52 v3 v + 1 .8 /2.5 /3.3 v c m l output powe r s u pp l y supp ly - 53 vp p + 1 .8 /2.5 /3.3 v c m l output powe r s u pp l y supp ly - 54 vp p d escript i on st y l e i/o pa d n o . pa d tabl e 22: sig n al pin defin i tions (conti nued) note 1: in te rna l 40 k oh m pu ll-up to vcc note 2: pad func tiona lity p r og ra mmed thr ough se r i a l in ter f ace note 3: se lec t ab le c m o s o r ope n - dra i n output s t yle note 4: t w o pads on the ic e x is t w i th the sa me na me . the y a r e ele c tr ica lly equ iva l ent and on ly one should be conn ected.
data sheet ZL62024 page 17 zarlink semiconductor inc. figure 9: p a d lay out diagram r x _o u t 2_p r x _o u t 2_n r x _o u t 1_p rx_ o ut 1 _ n r x _o u t 0_p r x _o u t 0_n r x _o u t 3_p r x _o u t 3_n gnd3 v mo n i t o r vpp vp p v 3 v v3 v gn d3 v gn d 3 v vpp vp p v 3v v3 v a drs 0 g n d3v g nd3vi v3 v i v3vi rx _ e n sd data ad rs 1 cl k gnd 3 v gnd 3 v i g nd3vi gn d3 vi v3 v i v3 v i rx _ e n sd da t a cl k gnd 3 v gn d3 v a c d dc 1 10 20 30 40 54 d e t _ bi as4 gn d3 v i rx_ i n0 rx_ i n1 rx _ i n 2 rx_ i n3 gn d3 v i d e t _ bi as3 det_ bi as2 d e t _ bi as1 gn d3 v i d e t _ bi as0 50 z arl i n k z l 620 44 b ta ble 23 : c r i t i cal d i m e ns ions s y m b o l d e s c r i pt i o n l e ngt h un i t a p a d t o pa d pi t c h 1 25 um b b on d pad l e ng t h / w i d t h 11 4 u m c c orne r p a d t o c o r n e r pa d pi t c h 1 2 5 u m d p ad c ent er t o ed ge of di e 1 2 2 . 5 u m x o v e r a l l i c di m e ns i o n s 22 45 + / - 2 5 u m y o v e r a l l i c di m e ns i o n s 18 70 + / - 2 5 u m z s t a nd ar d d i e t h i c k n e s s 1 7 m i l s
www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at

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